1. Field of the Invention
The present invention relates to a suitable memory access control method and system for realizing the same used in a personal computer.
2. Description of the Related Art
In accordance with the progress of a semiconductor technology, microprocessors and memory LSIs have been supplied at extremely low cost. Also, the performance thereof has been remarkably improved. Particularly in the field of the microprocessor, the bit width has been extended in order that an 8-bit processing, a 16-bit processing, and a 32-bit processing can be simultaneously performed, resulting in a high-speed processing. As such a typical microprocessor, iAPX86 (8086), iAPX88 (8088), iAPX186 (80186), iAPX286 (80286), iAPX386 (80386), manufactured by Intel Corp. U.S.A., have been normally used in the field of the personal computer.
For example, iAPX 286 can be operated in two different modes, that is, a real address mode and a protected virtual address mode. In the real address mode, iAPX286 operates as iAPX86 (8086) with high performance. In this case, memory up to 1 mega bytes (MB) can be accessed. Programs, which are written for iAPX86 or iAPX186, can be executed without making any modifications. Moreover, in the protected mode, a memory access having 1 MB or more can be gained, and all functions of iAPX286 can be performed. These functions include a data protection, a system integration, a task simultaneous processing, and a memory management including a virtual memory. In an initial state after a system reset, a processor starts operating in the real address mode. In the real address mode, all memory addressing is executed as a physical real address. When iAPX286 operates in the real address mode, a memory space of 1 MB (2.sup.20 bytes) can be addressed similar to the other processors in the iAPX86 family. The physical address is constituted by 20 bits, and each byte in the address space is identified by an inherent address. In other words, the physical addresses are set in the range of 0H-FFFFH. One address is designated by a pointer of 32 bits, and the pointer comprises the following two elements:
(1) 16-bit effective address offset which shows a specific position in a segment as a segment inner displacement in units of bytes; and PA1 (2) 16-bit segment selector which shows a start address of the segment.
Since the size of one segment is 64K bytes in maximum, 16-bit (unsigned) effective address offset is sufficient to address an arbitrary one byte in the segment. The offset of the first address in the segment is 0 and the offset of the last address is FFFFH. The 16-bit segment selector designates which part in the physical space of 2.sup.20 bytes the start address of the segment is. In the real address mode, iAPX286 always generates the physical address of 20 bits by the values of the segment selector and the offset.
For example, in a case where an application program, which is prepared by iAPX86 microprocessor, is executed by iAPX286 microprocessor having a memory address space of 1 MB or more, it is necessary to inhibit the memory access of 1 MB or more. In iAPX286 microprocessor, a protection enable bit is provided, iAPX286 is constituted to be operated in the real address mode when the protection enable bit is in a reset state. However, since addresses A0-A24 are electrically provided (an address bus of A0-A24 is provided), there is a possibility that address A20 will become "1" by influence of noise. Accordingly, even in the real address mode, there is a possibility that the memory access to 1 MB or more will be accessed.
A mechanism will now be described for preventing i8036 CPU from accessing a memory of 1 MB or more in the real address mode by using a control signal of a keyboard controller (KBC).
As shown in FIG. 1, for example, if the segment of the memory address is "FFFF" H, and the offset is "FFFF" H (wherein H shows an indication of Hexadecimal), the address computation result exceeds 1 MB. Specifically, since "FFFF" is multiplied by 16 in the segment address and 4-bit-shifted to the left, "FFFF0" and "FFFF" are added. The bit (bit 20 of the memory address) of A20, which indicates 1 MB, becomes 1. In this case, if the microprocessor i8086 is used as CPU, the address bus is constituted by lines A0 to A19 and the address computation result (computation result of the offset address and the segment address) is recognized as "0FFFF" H, and the address returns to the start of the memory and is accessed therefrom.
However, in a CPU using a microprocessor introduced after the i8086, if the address computation result exceeds 1 MB, the microprocessor recognizes this bit because of the presence of A20, memory access of 1 MB or more is performed even if the CPU is in the real address mode. As a result, the program does not normally operate. To eliminate this situation, keyboard controller KBC outputs a control signal in response to a command and data from the CPU. The control signal gates the A20 signal even if the CPU outputs an address exceeding 1 MB or more and the A20 signal is effective as a result of the address computation.
FIG. 2 is a schematic block diagram of the abovementioned and conventional memory access control system. In FIG. 2, a system comprises a CPU 31, a KBC 32, a register (input and output port) 33 in KBC 32, a status register 34 indicating the status of KBC, and AND gate 35 controlling A20 signal. Even if A20 signal is output at "HIGH" level, A20 signal does not pass through the gate 35 and memory of 1 MB or more is not accessed if CPU 31 accesses KBC 32 in advance so that a real signal, which is output from KBC 32, is set at "LOW" level. In other words, changing the REAL signal from "LOW" to "HIGH" means that the mode is changed from the real address mode to the protected virtual address mode. Moreover, changing the real signal from "HIGH" to "LOW" means that the mode is changed from the protected virtual address mode to the real address mode. In this case, to set the REAL signal to "LOW" level, CPU 31 first sends command "D1" H to the register 33 (input and output port having an address of designated by "64" H) in KBC 32 to inform KBC 32 of data write (IOW). At this time, a bit indicating an input buffer full of the status register 34 in KBC 32 becomes "1". After the processing of command "D1" is finished by a firmware provided in KBC 32, this bit becomes "0". After reading this bit of "0", CPU 31 writes data to KBC 32 again. If CPU 31 sends data "DD" H to the input and output (I/O) port "60" H of KBC 32, a REAL signal becomes "LOW". Moreover, if CPU 31 sends data "DF" H thereto, the REAL signal becomes "HIGH."
When the CPU 31 changes the REAL signal for controlling the memory access output from KBC 32 from HIGH to LOW or from LOW to HIGH, the CPU 31 must wait for a period of time from its write request before it can transmit data to KBC 32 and complete the process. It must wait from the time when the CPU 31 sends the write request command to KBC 32 until the time when the CPU 31 is enabled by the KBC 32 to send the data for changing the control signal, i.e., until the processing of the write request command is completed by the KBC 32. In other words, the CPU 31 must wait before it can transmit data to KBC 32 for a period of time during which the "input buffer full" bit remains "1" as a result of the data write command from the CPU 31. It is only when the firmware completes the command processing and sets the "input buffer full" bit to "0" that the CPU 31 is enabled to write data to KBC 32.